Kiran Kumar Jallada

Kiran Kumar Jallada

· 15+ years of experience in ASIC front end from Logic Verification to Synthesis · Developed Verification TB Environment... | Hyderabad, Hyderabad, India

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Work Experience

Amd

Smts

Sat May 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Invecas

Smts

Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Odc Cw Lead (Invecas)

Fri Jan 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Odc Contractor(Soctronics) - Smts

Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Odc Contractor(Soctronics) - Mts

Fri Jul 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Soctronics

Mts/ Project Lead

Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Imagination Technologies

Sr. Engineer(Contractor)

Tue Oct 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Soctronics

Sr Engineer

Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Sr Asic Engineer / Sr Engineer

Tue Nov 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Asic Engineer

Tue Dec 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

Soctronics

Asic Engineer

Sat Nov 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)

Gd Micro Systems

Asic Engineer Trainee

Wed Nov 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

Veda Iit

Advanced Diploma In Vlsi Logic Design

Mon May 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

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